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Carrier mobility enhancement through local strain in silicon is a means of improving transistor performance. In order to effectively validate device design and process conditions, a direct measurement of strain in the nanoscale is desired. Here, we demonstrate true nanoscale strain mapping via PiFM on SiO2 regions that are sandwiched by SiGe lines. Inverted PiFM profile across the line drawn in the left image shows the level of strain in arbitrary units; we can see that the strain is greatest at the SiGe lines and relaxes away from the SiGe lines. In between the two SiGe lines, the strain is frozen, whereas the strain is completely gone about 400 nm away from the SiGe line.
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